Bcd to excess 3 code converter

ABSTRACT

A binary coded decimal to excess 3 code converter is described which includes a plurality of EXCLUSIVE-OR gates and means for coupling the EXCLUSIVE-OR gates so that in response to BCD input signals the EXCLUSIVE-OR gates provide excess 3 coded output signals.

United States Patent Spani [54] BCD TO EXCESS 3 CODE CONVERTER [72] Inventor: Wayne Spani, San Diego, Calif.

[73] Assignee: Eastman Kodak Company,

Rochester,

[22] Filed: March 16, 1971 [21] Appl. NQL; 124,683

[52] US. Cl. ..23 5/l55, 340/347 DD [51] Int. Cl. ..H04l3/00 [58] Field of Search "235/155, 92; 340/347 DD [56] References Cited 7 I I UNITED STATES PATENTS 2,877,447 3/1959 Kenrichr; ..33s/1s5 3,153,228 l0/1964 Winkler .L ..235/l55 1151 3,706,880 [451 Dec. l9, 197 2 OTHER PUBLICATIONS Frim & Miller, Here Are More Digital Converters,"

Electronic Design 25, Dec. 6, 1969 pg 86, Scientific Library Primary Examiner--Daryl W. Cook Assistant Examiner-Jeremiah Glassman Attorney-W. H. J. Kline and Raymond L. Owens [5 7] ABSTRACT 6 Claims, 1 Drawing Figure PATENTED BEL 1 9 I972 EIS WAYNE SPAN! INVENTOR.

mz am ATTORNEYS I BCD TO EXCESS 3 CODE CONVERTER cRoss REFERENCE To RELATED APPLICATIONS Reference is made to commonly assigned copending US. Pat. application, Ser. No. 124,684, entitled Excess 3 to BCD Code Converter, filed contemporaneously herewith in the name of ,Wayne Spani.

BACKGROUND OF THE INVENTION The present invention relates to code converting apparatus and particularly to binary coded decimal to excess3 code converters.

One of the most commonly used codes in computing apparatusis the-binary coded decimal code (BCD). Often within computing apparatus, the BCD code is converted to the excess: 3 codewhich is particularly useful where it is desired to perform arithmetic opera: tions by the method of compliments. A conventional BCD to excess 3 code converter using 13 logic gates is shown on page 86 of Electronic Design, Vol. 17, No. 25, Dec. 6, 1969, which was designed by a systematic procedure employing Karnaugh maps.

SUMMARY OF THE INVENTION In the disclosed embodiment of the invention, a BCD to excess 3 converter includes a plurality of EXCLU- SIVE-OR gates adapted to receive as inputs binary code decimal input signals 1,, 1 I and I and circuit 1 means for coupling the EXCLUSIVE-OR gates so that BRIEF DESCRIPTION OF THE DRAWING In the detailed description of the preferred embodiment of the invention presented below, reference is made to the accompanying drawing which depicts a block diagram of a BCD to excess 3 code converter in accordance with the invention. The symbols for the logic components shown in. the drawing are in accordance with the American Standard Graphical Symbols for Logical Diagrams (ASA Y 32.14-1962).

DESCRIPTION OF THE PREFERRED EMBODIMENT To facilitate an understanding of the present invention,'the BCD and excess 3 codes will be first briefly reviewed in conjunction with Tables I and II which show for the decimal digits through 9 (left column) the BCD and excess 3 equivalent respectively.

TABLEI Binary Coded Decimal Code Decimal Digit l 4 [I TABLE II ExcessSCode Decimal Digit 0 0. O, O,

As shown by Table ll, theexcess 3 code is a self-complementing code. More specifically, the nine's compliment of a decimal digit expressed in excess 3 code may be obtained by complimenting each particular individual bit. For example, for the decimal digit 1, the excess 3 code representation is the number 0100 whose compliment on an individual bit basis is 1011 which in the excess 3 code has a decimal equivalent of 8.

Referring now to the drawing, there is shown a BCD to excess 3 code converter 10 having a plurality of I input terminals for a plurality of binary input signals 1,, 1 I and I respectively and a plurality of output terminals for a plurality of excess 3 output signals 0,, O

O and O, respectively. The converter 10 includes a- Referring specifically to the drawing, EXCLUSIVE- OR gate 12 is responsive to only the input signal I, and thus provides an inverter function. The gate 12 provides the output signal 0, to satisfy equation 1. The EXCLUSIVE-OR gate 12 could be replaced by a signal inverter and still solve equation 1. The output of the gate 12 is also provided as an input to the EXCLU- SIVE-OR gate 14 and a NAND gate 20. The EXCLU- SlVE-OR gate 14 also receives input signal I, and provides output signal 0, which satisfies equation 2. In addition, the output of gate 14 is provided to the NAND gate 20 which produces a first reference signal having the Boolean representation [(l" I I,] which can be simplified to the expression (1, I The NAND gate 20 is directly coupled to the EXCLUSIVE-OR gate 16 and an AND gate ZZJEXCLUSIVE-OR gate- 16 also is responsive to the input signal I; and produces the outa put signal O which satisfies equation 3.

correct selection of a number of other combination of gates. T 1

The invention has been described in detail with par-' be understood that variations and modifications can be effected within the spirit and scope of the'invention.

I claim:

1. In a BCD to excess 3 code converter for converting binary input signals l l l and l to excess 3 output-signals O 0,, prising: e

a. a plurality of EXCLUSIVE-OR means;

b. circuit means defining a plurality of input terminals for the binary input signals l l l and l and a plurality of output terminals for excess 3 output signals 0,, O O and and v means for coupling said EXCLUSIVE-R means to said terminals to establish the following Boolean relationships between the input signals and the output signals:

2. In a BCD'to excess 3 code converter for converting binary input signals l l l and -i to excess 3 output signals 0,, O O and 0 the combinationcom- O and 0 the combination com- EXCLUSIVE-OR function may also be realized by the v ticular reference to a'lpreferred embodiment but it will 4 prising:

a. at- I responsive to a selected one of the BCD input signals and adapted to provide a selected output signal; and

b. means couplingtheEXCLUSIVE-OR gates to satisfy the following Boolean relationships 3. ln a BCD to excess '3 codeconverter for convertprising:

.a. inverting means responsive to the 1 signal for providing the 0 signal;

b. first EXCLUSlVB-OR gate means responsive to the I, and 0 signal for'providing the 0, signal;

c. means responsive to O, and O, signals to provide a first reference signal; d. second EXCLUSIVE-0R gate means responsive to the 1 signal and said first reference'signal" to 'rovide the O si 'nal' e. rneans responsiv to 'said first reference signal and the 1 signal to provide' a second reference signal;

' and f. third EXCLUSIVE-OR gate means responsive to said second reference signal and the l signal to provide the 0 signal. a v 4. The invention as set forth in claim 3 wherein said inverting means comprises an EXCLUSlVE-OR gate.

5. The invention as set forth in claim 3 wherein said first reference signal providing means comprises a NAND gate. I

' 6. The invention as set forth in claim 5 wherein said second reference signal providing means comprises and AND gate.

least three EXCLUSIVE-OR gates, ac]. 

1. In a BCD to excess 3 code converter for converting binary input signals I1, I2, I4, and I8 to excess 3 output signals O1, O2, O4, and O8, the combination comprising: a. a plurality of EXCLUSIVE-OR means; b. circuit means defining a plurality of input terminals for the binary input signals I1, I2, I4, and I8 and a plurality of output terminals for excess 3 output signals O1, O2, O4, and O8; and c. means for coupling said EXCLUSIVE-OR means to said terminals to establish the following Boolean relationships between the input signals and the output signals:
 1. O1 I1
 2. O2 I2 + I1
 2. O2 I2 + I1
 2. O2 I2 + I1
 2. In a BCD to excess 3 code converter for converting binary input signals I1, I2, I4, and I8 to excess 3 output signals O1, O2, O4, and O8, the combination comprising: a. at least three EXCLUSIVE-OR gates, each responsive to a selected one of the BCD input signals and adapted to provide a selected output signal; and b. means coupling the EXCLUSIVE-OR gates to satisfy the following Boolean relationships between the input and output signals:
 3. O4 I4 + (I2 + I1)
 3. In a BCD to excess 3 code converter for converting binary input signals I1, I2, I4, and I8 to excess 3 output signals O1, O2, O4, and O8, the combination comprising: a. inverting means responsive to the I1 signal for providing the O1 signal; b. first EXCLUSIVE-OR gate means responsive to the I2 and O1 signal for providing the O2 signal; c. means responsive to O1 and O2 signals to provide a first reference signal; d. second EXCLUSIVE-OR gate means responsive to the I4 signal and said first reference signal to provide the O4 signal; e. means responsive to said first reference signal and the I4 signal to provide a second reference signal; and f. third EXCLUSIVE-OR gate means responsive to said second reference signal and the I8 signal to provide the O8 signal.
 3. O4 I4 + (I2 + I1)
 3. O4 I4 + (I2 + I1)
 4. O8 I8 + I4 (I2 + I1)
 4. O8 I8 + I4 (I2 + I1)
 4. O8 I8 + I4 (I2 + I1)
 4. The invention as set forth in claim 3 wherein said inverting means comprises an EXCLUSIVE-OR gate.
 5. The invention as set forth in claim 3 wherein said first reference signal providing means comprises a NAND gate.
 6. The invention as set forth in claim 5 wherein said second reference signal providing means comprises and AND gate. 